Q & A Q & A VLSI

⨘ } Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?

This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, something more deeper related to device physics.

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