Either is good. North American companies prefers Verilog/SystemVerilog and European companies prefer VHDL. Each has it own advantages and disadvantages. One need to know fundamentals of writing a good RTL code. Modern EDA tools can synthesize RTL code written in either language as long as synthesizable constructs are used.
I have answered this question on Quora: https://www.quora.com/Which-ASIC-language-should-I-focus-on-Verilog-2005-SystemVerilog-VHDL-or-other-for-ASIC-SYNTHETIZABLE/answer/H-Rajput-3
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