Q & A Q & A VLSI

⨘ } What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?

There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, second, we need to check whether data is passing from faster clock to slower or vice versa. We need to make sure of data stability as well, we need to understand intent of design and need to use proper CDC solution, e.g.closed-loop, fifo etc.

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