This lecture discusses multi voltage domain crossings. Now a days integrated circuits are no longer simple circuits running on one or two static voltage domains but having dynamically switched multi voltage domains. Signals pass through these voltage domains. There can exists crossings between different clock domains having same voltage domain or different clock domains and different voltage domains or same clock domains but different voltage domains. This becomes quite important to pay attention to these crossings otherwise these crossing may screw things up in your chip. This lecture discusses design techniques for voltage domain crossings, clock domain verification under multi voltage scaling. Typically UPF (unified power format) based CDC flow is used to properly verify along with manual checks such kind of design issues. Typical techniques for multi-VDD designs use level shifters, multiplexers controlled by power control logic, and or retention cells.
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