This lecture discusses reset domain crossing (RDC) digital design techniques. Reset trees are similar to clock trees and resets crossings must be carefully verified. It needs to plan early in the design phase for clock and reset crossing verification which is quite essential. The bugs which can be due to reset domain crossings or clock domain crossings can screw things up and chip may not work. Typically these kind of bugs due to RDC or CDC are skipped in functional verification and it becomes important to use electronic design automation software tools to catch those errors due to RDC and CDC. In a typical chip there are many reset domains and signal cross from one domain to another. It is similar to clock domain crossings. Both CDC and RDC verification is typically done together. One can use industry standard tools such as Mentor’s 0-in (quest cdc and questa resetcheck) tools to verify clock and reset crossings.
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