Tutorials

Tutorials

• ⨘ } VLSI } coding Techniques – a simple fifo design in verilog / system verilog
  https://youtu.be/uETKhaT77g4  158 total views,  2 views today
• ⨘ } VLSI } Reconvergence, CDC
  https://youtu.be/ycAMZN1Idz0  182 total views
• ⨘ } VLSI } 23 } Transmission Gate Logic Circuits } LE PROFESSEUR }
  Transmission gate logic style offers certain advantages over pass-transistor logic. We discuss about transmission logic gate concepts, how can we ...
• ⨘ } Powerful Charting Tool for Stock Analysis
  Realtime chart for stocks  978 total views,  1 views today
• ⨘ } VLSI } 22 } Pass-transistor logic circuits
  nmos/pmos transistors can be used in a configuration where voltage on gate can be think in terms of control or ...
• ⨘ } Complex Concepts Made Easy } LEPROFESSEUR }
  Complex Concepts Made Easy – LEPROFESSEUR / LEPROF / 1LEPROF https://youtu.be/OTmxdVlitaU  1,796 total views,  2 views today
• ⨘ } Multi-criteria Decision Making, Analytical Hierarchy Process (AHP) } LEPROF }
  Analytical Hierarchy Process (AHP) is a well known method for making qualitative decisions. AHP provides formal technique for evaluating alternatives ...
• ⨘ } awk miscellaneous commands
  1. Extract pattern from file and do sum of all entries matching the pattern grep ” Sequential ” idle_power.txt ...
• ⨘ } VLSI } CMOS Circuits, Physical Layout, Combinatorial Logic Gates } LEPROF }
  We have discussed logic gates in the previous lecture: Logic gates using multiplexers. We discussed at logic gate level. In ...
• ⨘ } Math Equations in Keynote / LaTeX
  Apple Keynote takes Latex format equations. Some useful commands are below. x^2 + y^2 = z^2 If you like to have subscripts x_n^2 ...
• ⨘ } How to use extract_model_split_partial_clock_gating_arc variable in PrimeTime ?
  extract_model_split_partial_clock_gating_arc variable controls whether to split clock gating setup and hold arcs in extracted timing model (ETM). Default value of ...
• ⨘ } Powerful charting tool for FOREX, CFDs, and Bitcoin
  Realtime chart for FOREX, CFDs, and Bitcoin  682 total views
• ⨘ } How do you fix a finite-state machine (digital logic, Verilog, logic gates, clock, small electronics, FSM, electronics)?
  For small state-machines it might be easy by looking at it, however for bigger state machines and interlinked state-machines just ...
• ⨘ } clearcase version control useful commands
  Set alias alias ct /usr/atria/bin/cleartool Version ct -ver List vob ct lsvob List views ct lsview ct lsview view-tag Create a tag ct mktag -view -tag ...
• ⨘ } Clock domain crossings – Reconvergence – What to do?
  Reconvergence – in simple terms signals are diverging from same end-point in Tx clock domain and going to multiple end-points ...
• ⨘ } vi / vim / gvim editor useful commands
  Some common settings you may want to keep in .vimrc file set number set backspace=indent,eol,start set hlsearch set shiftwidth=3 set tabstop=3  4,641 total views,  10 views today
• ⨘ } Which ASIC language should I focus on? Verilog 2005, SystemVerilog, VHDL or other? “for ASIC SYNTHETIZABLE”.
  Either is good. North American companies prefers Verilog/SystemVerilog and European companies prefer VHDL. Each has it own advantages and disadvantages. ...
• ⨘ } Which one is better? A PhD or a 2nd master’s?
  I think, one needs to know first where they want to see themselves 10–15 years future in life. Double Masters ...
• ⨘ } How Hard is PhD ?
  Totally depends on what is individual’s situation is. Typically it takes between 6–7 years in American reputed universities. Every university ...
• ⨘ } Is there any approach of automatically detect Async Fifo in scope of CDC ?
  This question was asked by “Vazgen Gyoletsyan” on youtube leprofesseur channel. My impression is that modern CDC tools in their reports ...
• ⨘ } Real Time FOREX Calculator
  Currency Converter by OANDA  1,242 total views,  2 views today
• ⨘ } Greater Toronto’s Real Estate House Prices Setting Record – is there a signal before storm ?
  Toronto’s house prices are touching record breaking heights since pandemic started. Is this a signal before storm ? What do ...
• ⨘ } extract a pattern from file – perl
  #!/usr/bin/perl use strict; use warnings; open my $FH, ‘<‘, $ARGV $!\n”; open my $EXT_FH, ‘>’, $ARGV or ...
• ⨘ } git version control useful commands
  1. clone from repository git clone $GIT_REPOS/ip cloned-ip where: $GIT_REPOS is path to git repository if you like to ...
• ⨘ } Linux / Unix useful commands
  1. compress and archive the directory / folder tar -zcvf /home/folder.tar.gz /home/folder where: z: compress archive using gzip program c: create ...
• ⨘ } recursive folder structure based on excel spreadsheet information – perl
  Below a simple perl script to make directory folder structure which may be helpful for you if you need to ...
• ⨘ } Hedge fund strategies – in theory.
  Hedge funds have become very popular among very wealthy communities as preferred medium of investment. To our knowledge there is ...
• ⨘ } Banks vs Credit Unions – which is better for you ?
  A brief discussion on Banks vs Credit unions. Banks: 1) Typical higher monthly account fees, e.g. $5-$10 for basic chequing account. There ...
• ⨘ } VLSI } 20 } CMOS Interconnects }
  Wire connecting the devices (nmos, pmos) are normally referred to as interconnects. Interconnects are very important, almost 70 percent chip ...
• ⨘ } LUP Decomposition: why do we need the P? Why the LU will give us a wrong result?
  “P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero ...
• ⨘ } Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?
  In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must ...
• ⨘ } Clock Domain Crossing: When the data is crossing from slower clock (source domain) to faster clock (destination domain) which technique can be used?
  When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, ...
• ⨘ } Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?
  This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, ...
• ⨘ } Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?
  Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before ...
• ⨘ } What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?
  There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, ...
• ⨘ } Error with gEcon installation on Apple MAC
  error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there ...
• ⨘ } Antenna Effects – Can jumpers be in higher and lower metal both?
  different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it ...
• ⨘ } How tap cells remove latch-up?
  n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library ...
• ⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }
  We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be ...
• ⨘ } VLSI } 18 } Mentor’s Questa CDC Analysis } 0in }
  Siemens / Mentor’s Questa 0-in clock domain crossing (CDC) solution – how to use Questa CDC tool, what are different ...
• ⨘ } VLSI } 017 } CMOS Power Consumption }
  CMOS power and energy concepts, power analysis during chip design flow is discussed. AC and DC power are discussed. Different ...
• ⨘ } VLSI } 016 } Do You Write a Good RTL Code }
  Important concepts for a good RTL design, blocking, non-blocking type of statements in verilog, multiple-drivers, assertions, fsm-deadlock, and in general ...
• VLSI } 015 } Static Timing Analysis
  This lecture discuss static timing analysis concepts. What are different paths, different kinds of checks, e.g. max type, min type ...
• VLSI } 014 } Latch-up & CMOS Technologies }
  Latch-up phenomenon in CMOS circuits – What is latch-up, what are typical methods to mitigate latch-up and layout changes ...
• VLSI } 013 } Floor-planning tips }
  This lecture discusses some of the SoC floor-planning challenges and tips. A good floor-plan is the key to quality placement ...

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