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Q & A Q & A VLSI

⨘ } How to use extract_model_split_partial_clock_gating_arc variable in PrimeTime ?

extract_model_split_partial_clock_gating_arc variable controls whether to split clock gating setup and hold arcs in extracted timing model (ETM). Default value of this variable is FALSE. Setting of this variable affects all formats e.g. synopsys database (.db), liberty (.lib) formats. This variable can be set to either TRUE or FALSE. FALSE: merges all clock gating checks and […]

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Categories
Computing VLSI

VLSI } 015 } Static Timing Analysis

This lecture discuss static timing analysis concepts. What are different paths, different kinds of checks, e.g. max type, min type timing analysis tool like prime time from synopsys does. How the setup and hold checks are performed, how to analyzed the timing report, how to fix the setup and hold violations are discussed. The need […]

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Categories
Computing VLSI

VLSI } 006 } Timing }

This lecture discusses timing in digital circuits. It is said that “Timing is everything”. If someone does not arrive on time at a meeting of a party it is considered bad effect. In similar way timing is the most important in digital circuits. Sequential digital techniques are dependent on correct time accurate behavior of design […]

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