Categories
Q & A Q & A VLSI

⨘ } Is there any approach of automatically detect Async Fifo in scope of CDC ?

This question was asked by “Vazgen Gyoletsyan” on youtube leprofesseur channel. My impression is that modern CDC tools in their reports provide detailed information that can be scripted to know various information related to clock domain crossings in the full chip design.  946 total views,  5 views today

 946 total views,  5 views today

Categories
Q & A Q & A VLSI

⨘ } What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?

There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, second, we need to check whether data is passing from faster clock to slower or vice versa. We need to make sure of data stability as well, we need to understand intent of design and […]

 2,579 total views

Categories
Computing VLSI

VLSI } 010 } Reset Domain Crossing (RDC) }

This lecture discusses reset domain crossing (RDC) digital design techniques. Reset trees are similar to clock trees and resets crossings must be carefully verified. It needs to plan early in the design phase for clock and reset crossing verification which is quite essential. The bugs which can be due to reset domain crossings or clock […]

 6,349 total views,  2 views today