Tag: cmos latch-up

⨘ } How tap cells remove latch-up?

Post author By LEPROF
Post date 7th November 2019
No Comments on ⨘ } How tap cells remove latch-up?

n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library with uniform height (certain advantages such as reduce std cell size, and so pack more cells in a given area), means those cells in same row can share well-ties (done via TAP cells), which can […]

4,230 total views

Tags cmos, cmos latch-up

Computing VLSI

VLSI } 014 } Latch-up & CMOS Technologies }

Post author By LEPROF
Post date 1st August 2017
No Comments on VLSI } 014 } Latch-up & CMOS Technologies }

Latch-up phenomenon in CMOS circuits – What is latch-up, what are typical methods to mitigate latch-up and layout changes for conventional bulk silicon technology. A discussion on other technology – SOI versus bulk silicon is presented. 5,563 total views

5,563 total views

Tags cmos latch-up