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Computing VLSI

⨘ } VLSI } 22 } Pass-transistor logic circuits

nmos/pmos transistors can be used in a configuration where voltage on gate can be think in terms of control or valve to pass water (electric current analogue) between terminals of transistor, pass-transistors logic concepts are discussed. How pass transistors are different than conventional CMOS logic circuits, advantages, disadvantages of pass-transistor logic are discussed with examples […]

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Categories
Computing VLSI

⨘ } VLSI } CMOS Circuits, Physical Layout, Combinatorial Logic Gates } LEPROF }

We have discussed logic gates in the previous lecture: Logic gates using multiplexers. We discussed at logic gate level. In this lecture we gonna be discussing next level – gate circuits. Techniques to design logic gate circuits using nmos and pmos. Concepts of CMOS circuit design with nMOS and pMOS are discussed. We can think […]

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Q & A Q & A VLSI

⨘ } How tap cells remove latch-up?

n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library with uniform height (certain advantages such as reduce std cell size, and so pack more cells in a given area), means those cells in same row can share well-ties (done via TAP cells), which can […]

 4,230 total views