Tag: clock domain crossing

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Q & A Q & A VLSI

⨘ } Clock domain crossings – Reconvergence – What to do?

Reconvergence – in simple terms signals are diverging from same end-point in Tx clock domain and going to multiple end-points in Rx clock domain(s). See attached fig. What can we do in this situation? First of all it is an important issue which needs to be carefully reviewed. There can be different approaches to mitigate […]

 1,878 total views

Categories
Q & A Q & A VLSI

⨘ } Is there any approach of automatically detect Async Fifo in scope of CDC ?

This question was asked by “Vazgen Gyoletsyan” on youtube leprofesseur channel. My impression is that modern CDC tools in their reports provide detailed information that can be scripted to know various information related to clock domain crossings in the full chip design.  2,711 total views

 2,711 total views

Categories
Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?

In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must fulfill minimum pulse width requirements in the receiving faster clock domain. If source clock is minimum 1.5x slower than destination clock, it is safe, one does not need special logic in source domain. In both […]

 4,350 total views

Categories
Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from slower clock (source domain) to faster clock (destination domain) which technique can be used?

When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, implementation must fulfill minimum pulse width requirements in slower clock. One may implement open loop state machine based solution in faster clock domain or some mechanism which makes sure to fulfill minimum pulse width requirement. […]

 4,130 total views

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Q & A Q & A VLSI

⨘ } Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?

This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, something more deeper related to device physics.  4,803 total views

 4,803 total views

Categories
Q & A Q & A VLSI

⨘ } Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?

Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before using them in design. Many designers simply use 2 or 3 regular d – flops for synchronization which is not a good design practice. Frequency ratio has nothing to do with the number of sync […]

 4,431 total views

Categories
Q & A Q & A VLSI

⨘ } What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?

There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, second, we need to check whether data is passing from faster clock to slower or vice versa. We need to make sure of data stability as well, we need to understand intent of design and […]

 4,159 total views