Categories
Computing VLSI

⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }

We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be verified. We discuss following topics: 1. Master asserts request signal to slave indicating communication initiation, and request signal should get asserted only after N number of clock cycles data signal is stable. 2. Slave’s grant […]

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Categories
Computing VLSI

Tutorials } System Verilog } Assertions }

This lecture discusses assertions in system verilog. Immediate, concurrent assertions with multiple clock domains are discussed. [ ►Subscribe ] Leprofesseur } on YouTube. We appreciate your feedback and support. Do not forget to give thumbs-up 🙂 Sincerely, H.  6,047 total views

 6,047 total views

Categories
Computing VLSI

Tutorials } System Verilog } A quick overview for verification }

This video lecture provides a quick concise overview about hardware verification environment and system verilog. At many universities this topic is not covered but very useful for industry. This video may help you very much if you wanna get a verification engineer job. Do not forget to subscribe { Leprofesseur } Channel on YoutTube by […]

 7,701 total views