Q & A Q & A VLSI

⨘ } Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?

Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before using them in design. Many designers simply use 2 or 3 regular d – flops for synchronization which is not a good design practice. Frequency ratio has nothing to do with the number of sync flops, ratio plays a role when we need to check pulse width for data stability, e.g. we want to make sure that data coming from faster domain does not get lost in slower clock domain. There are various techniques to ensure data stability. Please watch all clock domain crossing and metastability lectures ( to have more understanding on these issues.

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