extract_model_split_partial_clock_gating_arc variable controls whether to split clock gating setup and hold arcs in extracted timing model (ETM). Default value of this variable is FALSE. Setting of this variable affects all formats e.g. synopsys database (.db), liberty (.lib) formats.
This variable can be set to either TRUE or FALSE.
FALSE: merges all clock gating checks and attach them to same pin.
TRUE: detects clock gating setup and hold constraints, creates a separate internal pin to avoid differences in timing analysis with ETM.
Standard clock gating constraints pair setup on rise clock edge with hold on fall clock edge to ensue no clipping of positive clock pulse by gating signal. This pairing occurs automatically in PrimeTime. Sometime when proper pairing relationship can not be determined between rise and fall arcs, tool considered this as timing paths are not constrained. If setup is missing then hold is used as primary constraint.
As a compact timing model ETM retains most constrained relationship between input port and its related clock port from all paths that contribute to constraints. There are many paths and endpoints that contribute to constraints. By default this variable is set to false means merges all clock gating setup and hold arcs, and choses the worst among them.
To retain original arc relationship, internal pins need to be introduced to force split different classes of pairing on different pins. By setting extract_model_split_partial_clock_gating_arc to true, primetime creates internal pins and does timing analysis by imposing different classes of setup and hold pairs on different internal pins, a more accurate pessimistic analysis.
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