Q & A Q & A VLSI

⨘ } How tap cells remove latch-up?

n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library with uniform height (certain advantages such as reduce std cell size, and so pack more cells in a given area), means those cells in same row can share well-ties (done via TAP cells), which can be placed at regular intervals.

tap cells are placed at regular intervals depending on technology, it is not required to have each cell ties to tap cell, thus providing low resistance path for current to flow through.

 6,499 total views,  5 views today

Leave a Reply

Your email address will not be published. Required fields are marked *

This site uses Akismet to reduce spam. Learn how your comment data is processed.