Computing VLSI

⨘ } VLSI } CMOS Circuits, Physical Layout, Combinatorial Logic Gates } LEPROF }

We have discussed logic gates in the previous lecture: Logic gates using multiplexers. We discussed at logic gate level. In this lecture we gonna be discussing next level – gate circuits. Techniques to design logic gate circuits using nmos and pmos.

Concepts of CMOS circuit design with nMOS and pMOS are discussed. We can think about combinatorial circuits as two connected networks – pull-up network to pull the output to high and pull-down network to pull the output to low logic levels. Output is a function of inputs, with the values in the set {0,1}. pMOS are typically used in pull-up network to pull the output to high. nMOS are used in pull down network to pull output low. nMOS produce strong 0 when gate is connected to Vdd. pMOS produce strong 1 when gate is connected to ground. Together pMOS and nMOS produce desired behaviour of logic circuit output.
A layout and CMOS circuit of 2-input NAND gate is explained.

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