Q & A Q & A VLSI

⨘ } Clock domain crossings – Reconvergence – What to do?

Reconvergence – in simple terms signals are diverging from same end-point in Tx clock domain and going to multiple end-points in Rx clock domain(s). See attached fig.

What can we do in this situation?

First of all it is an important issue which needs to be carefully reviewed. There can be different approaches to mitigate the situation.

1. Logic change in Tx domain: Can we change logic so that we combine multiple signals from Tx domain and send only one signal to Rx domain? If that is feasible this would be a good solution. Sometimes it may not be feasible, in these scenarios can we find any other qualifier which can signify as when signals are stable in Rx domain, and that qualifier signals can synced and send across.

2. Logic change in Rx domain: Can we change logic so that only one signal out of group of divergent signals is used in Rx domain? If that is feasible then its good as we just need to sync the one signal and do not use other signals in Rx domain. This will solve the issue.

3. If it is not feasible to change logic in Tx or Rx clock domains, we may need to find qualifier signal which enables when Rx domain latched the data from Tx signals. This however may need a through design review as it can be dangerous if qualifier is not properly chosen.

In all the techniques we need to make sure data integrity as well. Signal sent from Tx domain is properly captured in Rx domain and there is no data loss.

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