When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, implementation must fulfill minimum pulse width requirements in slower clock. One may implement open loop state machine based solution in faster clock domain or some mechanism which makes sure to fulfill minimum pulse width requirement. Another better way is to implement a closed loop solution with some sort of acknowledgement from destination back to source clock domain that signal value has been correctly captured and the signal can carry new value. The state machine or some logic in faster clock domain needs to make sure that data pulse has been stretched enough that there will be no data loss in slower receiving domain.
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