Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?

In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must fulfill minimum pulse width requirements in the receiving faster clock domain. If source clock is minimum 1.5x slower than destination clock, it is safe, one does not need special logic in source domain.
In both cases crossing signal must pass through a sync flop mechanism (double flop of special sync cell from technology library). Further, one may develop assertions to verify CDC protocol for pulse width checks.

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