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Q & A Q & A Code

⨘ } awk miscellaneous commands

1. Extract pattern from file and do sum of all entries matching the pattern grep ” Sequential ” idle_power.txt | awk ‘{sum += $3} END {print sum}’ Here $3 is which column is to get sum of. Idea is to grep a certain pattern from file from each line and then process output by awk […]

 924 total views

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Q & A Q & A Code

⨘ } Math Equations in Keynote / LaTeX

Apple Keynote takes Latex format equations. Some useful commands are below. x^2 + y^2 = z^2 If you like to have subscripts x_n^2 + y_n^2 = z_n^2 Greek letters \alpha \beta \gamma \rho \sigma \delta \epsilon Operators \times \otimes \oplus \cup \cap < > \subset \supset \subseteq \supseteq \int \oint \sum \prod \times \div \cup […]

 535 total views,  2 views today

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Q & A Q & A VLSI

⨘ } How to use extract_model_split_partial_clock_gating_arc variable in PrimeTime ?

extract_model_split_partial_clock_gating_arc variable controls whether to split clock gating setup and hold arcs in extracted timing model (ETM). Default value of this variable is FALSE. Setting of this variable affects all formats e.g. synopsys database (.db), liberty (.lib) formats. This variable can be set to either TRUE or FALSE. FALSE: merges all clock gating checks and […]

 273 total views,  2 views today

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Q & A Q & A VLSI

⨘ } How do you fix a finite-state machine (digital logic, Verilog, logic gates, clock, small electronics, FSM, electronics)?

For small state-machines it might be easy by looking at it, however for bigger state machines and interlinked state-machines just by looking may not be easy to fix, there are EDA tools available which can identify stuck states, e.g. Mentor’s autocheck. Also by analyzing code coverage data one can review state machine coverage and identify […]

 302 total views,  2 views today

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Q & A Q & A Code

⨘ } clearcase version control useful commands

Set alias alias ct /usr/atria/bin/cleartool Version ct -ver List vob ct lsvob List views ct lsview ct lsview view-tag Create a tag ct mktag -view -tag tag-name Set a view ct setview view-name Print current view ct pwv List history ct lshistory file-name List private files ct lsprivate List checkout files ct lsco -r -l […]

 1,078 total views,  5 views today

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Q & A Q & A VLSI

⨘ } Clock domain crossings – Reconvergence – What to do?

Reconvergence – in simple terms signals are diverging from same end-point in Tx clock domain and going to multiple end-points in Rx clock domain(s). See attached fig. What can we do in this situation? First of all it is an important issue which needs to be carefully reviewed. There can be different approaches to mitigate […]

 329 total views

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Q & A Q & A Code

⨘ } vi / vim / gvim editor useful commands

Some common settings you may want to keep in .vimrc file set number set backspace=indent,eol,start set hlsearch set shiftwidth=3 set tabstop=3  1,153 total views

 1,153 total views

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Q & A Q & A VLSI

⨘ } Which ASIC language should I focus on? Verilog 2005, SystemVerilog, VHDL or other? “for ASIC SYNTHETIZABLE”.

Either is good. North American companies prefers Verilog/SystemVerilog and European companies prefer VHDL. Each has it own advantages and disadvantages. One need to know fundamentals of writing a good RTL code. Modern EDA tools can synthesize RTL code written in either language as long as synthesizable constructs are used. I have answered this question on […]

 308 total views

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Q & A Q & A VLSI

⨘ } Is there any approach of automatically detect Async Fifo in scope of CDC ?

This question was asked by “Vazgen Gyoletsyan” on youtube leprofesseur channel. My impression is that modern CDC tools in their reports provide detailed information that can be scripted to know various information related to clock domain crossings in the full chip design.  851 total views

 851 total views

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Q & A Q & A Code

⨘ } extract a pattern from file – perl

#!/usr/bin/perl use strict; use warnings; open my $FH, ‘<‘, $ARGV[1] or die “Could not open file: $ARGV[1] $!\n”; open my $EXT_FH, ‘>’, $ARGV[2] or die “Could not open file: $ARGV[2] $!\n”; while (my $line = <$FH>){ if ($line =~ /cabist|tap|fscan|fbscan|dangle) print $EXT_FH $line; } close $FH; close $EXT_FH;  796 total views,  5 views today

 796 total views,  5 views today

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Q & A Q & A Code

⨘ } git version control useful commands

1. clone from repository git clone $GIT_REPOS/ip cloned-ip where: $GIT_REPOS is path to git repository if you like to have little fancy to organize cloned versions with dates, i prefer this way: git clone $GIT_REPOS/ip ip-`date +%Y%b%d-%H%M` also you can further use alias to have this command as: alias hrclone “$GIT_REPOS/ip ip-hr-‘date +%Y%b%d-%H%M’” 2. list […]

 1,149 total views

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Q & A Q & A Code

⨘ } Linux / Unix useful commands

1. compress and archive the directory / folder tar -zcvf /home/folder.tar.gz /home/folder where: z: compress archive using gzip program c: create archive on linux v: verbose, show progress on screen f: archive file name 2. secure copy from remote server to local scp user_name@ip_address:/home/folder/file /local_dir/copied_files/ 3. secure copy from local to remote server scp /local_dir/file […]

 866 total views

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Q & A Q & A Code

⨘ } recursive folder structure based on excel spreadsheet information – perl

Below a simple perl script to make directory folder structure which may be helpful for you if you need to deal with thousands of folders. Example: folder_structure.csv (you may extract csv fromat from excel sheet). We need to make folder structure as continent folder contains regions, regions contains countries, each country contains states etc. ASIA,SOUTH […]

 601 total views

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Q & A Q & A Algorithms

⨘ } LUP Decomposition: why do we need the P? Why the LU will give us a wrong result?

“P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero element on U’s diagonal with only exception when all diagonal U are simultaneously zero.  2,905 total views

 2,905 total views

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Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?

In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must fulfill minimum pulse width requirements in the receiving faster clock domain. If source clock is minimum 1.5x slower than destination clock, it is safe, one does not need special logic in source domain. In both […]

 2,595 total views

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Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from slower clock (source domain) to faster clock (destination domain) which technique can be used?

When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, implementation must fulfill minimum pulse width requirements in slower clock. One may implement open loop state machine based solution in faster clock domain or some mechanism which makes sure to fulfill minimum pulse width requirement. […]

 2,524 total views

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Q & A Q & A VLSI

⨘ } Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?

This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, something more deeper related to device physics.  3,089 total views

 3,089 total views

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Q & A Q & A VLSI

⨘ } Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?

Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before using them in design. Many designers simply use 2 or 3 regular d – flops for synchronization which is not a good design practice. Frequency ratio has nothing to do with the number of sync […]

 2,843 total views

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Q & A Q & A VLSI

⨘ } What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?

There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, second, we need to check whether data is passing from faster clock to slower or vice versa. We need to make sure of data stability as well, we need to understand intent of design and […]

 2,474 total views

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Business Economics Q & A Q & A Economics

⨘ } Error with gEcon installation on Apple MAC

error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there before you try to make links,  3,218 total views

 3,218 total views

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Q & A Q & A VLSI

⨘ } Antenna Effects – Can jumpers be in higher and lower metal both?

different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it will increase net resistance and hence delay.  4,379 total views

 4,379 total views

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Q & A Q & A VLSI

⨘ } How tap cells remove latch-up?

n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library with uniform height (certain advantages such as reduce std cell size, and so pack more cells in a given area), means those cells in same row can share well-ties (done via TAP cells), which can […]

 3,386 total views

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Q & A Q & A Code

⨘ } vi Editor: quick guide }

This lecture provides a quick overview of vi editor.  6,152 total views

 6,152 total views