Category: VLSI

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Computing VLSI

⨘ } VLSI } coding Techniques – a simple fifo design in verilog / system verilog

 250 total views

 250 total views

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Computing Jumbled VLSI

⨘ } VLSI } Reconvergence, CDC

 254 total views

 254 total views

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Computing VLSI

⨘ } VLSI } 23 } Transmission Gate Logic Circuits } LE PROFESSEUR }

Transmission gate logic style offers certain advantages over pass-transistor logic. We discuss about transmission logic gate concepts, how can we design circuits using transmission gates, what are key advantages, disadvantages of transmission gates over traditional logic and pass-transistor logic styles with an example circuit design. Thanks for watching. ► SUBSCRIBE, Like 👍 , and press […]

 2,013 total views,  2 views today

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Computing VLSI

⨘ } VLSI } 22 } Pass-transistor logic circuits

nmos/pmos transistors can be used in a configuration where voltage on gate can be think in terms of control or valve to pass water (electric current analogue) between terminals of transistor, pass-transistors logic concepts are discussed. How pass transistors are different than conventional CMOS logic circuits, advantages, disadvantages of pass-transistor logic are discussed with examples […]

 1,224 total views,  4 views today

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Computing VLSI

⨘ } VLSI } CMOS Circuits, Physical Layout, Combinatorial Logic Gates } LEPROF }

We have discussed logic gates in the previous lecture: Logic gates using multiplexers. We discussed at logic gate level. In this lecture we gonna be discussing next level – gate circuits. Techniques to design logic gate circuits using nmos and pmos. Concepts of CMOS circuit design with nMOS and pMOS are discussed. We can think […]

 1,254 total views

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Computing VLSI

⨘ } VLSI } 20 } CMOS Interconnects }

Wire connecting the devices (nmos, pmos) are normally referred to as interconnects. Interconnects are very important, almost 70 percent chip area is consumed by interconnects. Interconnects increase circuit delays due to resistance and capacitances associated with them. Coupling capacitances induces crosstalk delay effects. Long wires induces inductive coupling due to inductance associated with them. Electric […]

 3,205 total views,  4 views today

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Computing VLSI

⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }

We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be verified. We discuss following topics: 1. Master asserts request signal to slave indicating communication initiation, and request signal should get asserted only after N number of clock cycles data signal is stable. 2. Slave’s grant […]

 3,199 total views,  4 views today

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Computing VLSI

⨘ } VLSI } 18 } Mentor’s Questa CDC Analysis } 0in }

Siemens / Mentor’s Questa 0-in clock domain crossing (CDC) solution – how to use Questa CDC tool, what are different clock domain crossing issues, different modes of operation of the tool, how to run the tool and generate CDC reports on full chip. Various aspects are discussed, e.g. what are common kinds of CDC violations, […]

 5,931 total views,  2 views today

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Computing VLSI

⨘ } VLSI } 017 } CMOS Power Consumption }

CMOS power and energy concepts, power analysis during chip design flow is discussed. AC and DC power are discussed. Different power components of PMOS and NMOS dynamic and static power are discussed. Static and Dynamic power equations are discussed. A brief overview of Apache Power Artist EDA power analysis tool is discussed. Dynamic power in […]

 5,192 total views

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Computing VLSI

⨘ } VLSI } 016 } Do You Write a Good RTL Code }

Important concepts for a good RTL design, blocking, non-blocking type of statements in verilog, multiple-drivers, assertions, fsm-deadlock, and in general good digital design practices are discussed. LEPROF/1LEPROF/LEPROFESSEUR  5,192 total views

 5,192 total views

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Computing VLSI

VLSI } 015 } Static Timing Analysis

This lecture discuss static timing analysis concepts. What are different paths, different kinds of checks, e.g. max type, min type timing analysis tool like prime time from synopsys does. How the setup and hold checks are performed, how to analyzed the timing report, how to fix the setup and hold violations are discussed. The need […]

 5,042 total views

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Computing VLSI

VLSI } 014 } Latch-up & CMOS Technologies }

Latch-up phenomenon in CMOS circuits – What is latch-up, what are typical methods to mitigate latch-up and layout changes for conventional bulk silicon technology. A discussion on other technology – SOI versus bulk silicon is presented.  6,000 total views

 6,000 total views

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Computing VLSI

VLSI } 013 } Floor-planning tips }

This lecture discusses some of the SoC floor-planning challenges and tips. A good floor-plan is the key to quality placement results. These are NP-hard problems which EDA tool have to deal with. A good initial floor-plan can save lot of physical design issues later in the design phase. It is very important to have a […]

 4,545 total views

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Computing VLSI

VLSI } 012 } Metastability }

This lecture discusses concept of metastability. Synchronous designs suffer from this inherent problem associated with flip-flops, latches in the design. How to conceptualize metastability. Water flow analogy is very helpful when designing circuits at transistors level. What is MTBF (mean time between failures) and how we can develop MTBF equation. What are different recommendations for […]

 5,974 total views

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Computing VLSI

VLSI } 011 } Clock Domain Crossing } Multi Voltage Domains }

This lecture discusses multi voltage domain crossings. Now a days integrated circuits are no longer simple circuits running on one or two static voltage domains but having dynamically switched multi voltage domains. Signals pass through these voltage domains. There can exists crossings between different clock domains having same voltage domain or different clock domains and […]

 5,542 total views

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Computing VLSI

VLSI } 010 } Reset Domain Crossing (RDC) }

This lecture discusses reset domain crossing (RDC) digital design techniques. Reset trees are similar to clock trees and resets crossings must be carefully verified. It needs to plan early in the design phase for clock and reset crossing verification which is quite essential. The bugs which can be due to reset domain crossings or clock […]

 7,259 total views,  2 views today

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Computing VLSI

VLSI } 009 } Clock Domain Crossings } FIFO }

This lecture extends the discussion on clock domain crossings. In this lecture design techniques for multi-bit clock crossings have been discussed. One can classify CDC signals in two groups broadly: control signals and data signals. For single bit control signals double flop synchronizing circuits or special library sync cells can be used safely. This becomes […]

 5,999 total views,  2 views today

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Computing VLSI

VLSI } 008 } Antenna Effects }

This lecture discusses concept of antenna effect in vlsi physical design. A typical chip manufacturing steps discussed with the design guidelines to avoid antenna effects in vlsi design. Antenna effect can damage the integrated circuit permanently. Antenna effects are caused by plasma etching process. In simple terms antenna are floating charge builds up on metal […]

 6,685 total views,  4 views today

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Computing VLSI

VLSI } 007 } Logic Gates using Multiplexers }

This lecture discusses multiplexers and logic gates. How to design logic gates using 2:1 multiplexers? Multiplexers are considered universal logic. One can design any logic gate using multiplexers and in turn any logic circuit. Mux-based FPGAS use these techniques to create logic gates using multiplexers for logic implementation. [ ►Subscribe ] Leprofesseur } on YouTube. […]

 5,555 total views,  2 views today

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Computing VLSI

Tutorials } System Verilog } Assertions }

This lecture discusses assertions in system verilog. Immediate, concurrent assertions with multiple clock domains are discussed. [ ►Subscribe ] Leprofesseur } on YouTube. We appreciate your feedback and support. Do not forget to give thumbs-up 🙂 Sincerely, H.  6,397 total views

 6,397 total views

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Computing VLSI

VLSI } 006 } Timing }

This lecture discusses timing in digital circuits. It is said that “Timing is everything”. If someone does not arrive on time at a meeting of a party it is considered bad effect. In similar way timing is the most important in digital circuits. Sequential digital techniques are dependent on correct time accurate behavior of design […]

 4,708 total views

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Computing VLSI

VLSI } 005 } State Machines }

This lecture discusses a fundamental and an important topic in digital circuit design – state machines. Mealy and Moore variants of sequential state machine are discussed with examples. How to synthesize state machine circuit from state graphs, state transition tables using Boolean equations and Karnaugh map is discussed. A verilog example for synthesizable Moore and […]

 7,846 total views,  2 views today

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Computing VLSI

VLSI } 004 } Clock-Domain-Crossing [CDC] Design Techniques }

This lecture discusses clock domain crossing (CDC) design techniques, single bit CDC signals, multi-bit CDC signals, 2-stage synchronizing flip-flops, 3-stage synchronizing flip-flops, meta-stability, MTBF, high-speed design considerations, and in general basic principles for multi-clock design. Do not forget to [ ►Subscribe ] { Leprofesseur } channel on YouTube. Sincerely, H.  11,198 total views

 11,198 total views

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Computing VLSI

VLSI } 003 } SoC design using cores and mixed-signal design aspects }

Practical concerns about system-on-a-chip design with respect to mixed-signal cores are discussed. It is difficult to design a mixed-signal IP core which works in silicon. Mixed signal design integrates two different kind of mind sets: digital and analog. In one world there is no concept of clock and other is totally dependent on clock signal. […]

 5,181 total views,  4 views today

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Computing VLSI

Tutorials } System Verilog } A quick overview for verification }

This video lecture provides a quick concise overview about hardware verification environment and system verilog. At many universities this topic is not covered but very useful for industry. This video may help you very much if you wanna get a verification engineer job. Do not forget to subscribe { Leprofesseur } Channel on YoutTube by […]

 8,059 total views

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Computing VLSI

VLSI } 002 } ASIC Design Automation Flow }

This video lecture describes EDA (Electronic Design Automation) tool flows. How the design idea of an integrated circuit is translated from concept to blue-print which leads to silicon. If you need private lessons/consultation you may contact at: hr@Leprofesseur.org Do not forget to subscribe { Leprofesseur } YouTube channel. Subscription helps to keep you up-to-date with […]

 5,111 total views

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Computing VLSI

VLSI } 001 } Design abstractions }

This video lecture discusses design abstractions, different levels in Gajski-Kuhn Y-Chart. If you like to have private lessons/tuition you may contact at hr@leprofesseur.org Do not forget to subscribe { Leprofesseur } YouTube channel. Sincerely, H.  5,586 total views

 5,586 total views