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Computing VLSI

⨘ } VLSI } 23 } Transmission Gate Logic Circuits } LE PROFESSEUR }

Transmission gate logic style offers certain advantages over pass-transistor logic. We discuss about transmission logic gate concepts, how can we design circuits using transmission gates, what are key advantages, disadvantages of transmission gates over traditional logic and pass-transistor logic styles with an example circuit design. Thanks for watching. ► SUBSCRIBE, Like 👍 , and press […]

 210 total views

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Tools

⨘ } Powerful Charting Tool for Stock Analysis

Realtime chart for stocks

 291 total views

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Computing VLSI

⨘ } VLSI } 22 } Pass-transistor logic circuits

nmos/pmos transistors can be used in a configuration where voltage on gate can be think in terms of control or valve to pass water (electric current analogue) between terminals of transistor, pass-transistors logic concepts are discussed. How pass transistors are different than conventional CMOS logic circuits, advantages, disadvantages of pass-transistor logic are discussed with examples […]

 335 total views

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Jumbled

⨘ } Complex Concepts Made Easy } LEPROFESSEUR }

Complex Concepts Made Easy – LEPROFESSEUR / LEPROF / 1LEPROF  208 total views

 208 total views

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Business Jumbled

⨘ } Multi-criteria Decision Making, Analytical Hierarchy Process (AHP) } LEPROF }

Analytical Hierarchy Process (AHP) is a well known method for making qualitative decisions. AHP provides formal technique for evaluating alternatives in presence of different criteria or attributes. Satty’s (1980) AHP technique is a pairwise comparison method which tries to capture relative judgements about attributes and alternative in a matrix form that ensure consistency. The simplicity […]

 269 total views

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Q & A Q & A Code

⨘ } awk miscellaneous commands

1. Extract pattern from file and do sum of all entries matching the pattern grep ” Sequential ” idle_power.txt | awk ‘{sum += $3} END {print sum}’ Here $3 is which column is to get sum of. Idea is to grep a certain pattern from file from each line and then process output by awk […]

 674 total views

Categories
Computing VLSI

⨘ } VLSI } CMOS Circuits, Physical Layout, Combinatorial Logic Gates } LEPROF }

We have discussed logic gates in the previous lecture: Logic gates using multiplexers. We discussed at logic gate level. In this lecture we gonna be discussing next level – gate circuits. Techniques to design logic gate circuits using nmos and pmos. Concepts of CMOS circuit design with nMOS and pMOS are discussed. We can think […]

 271 total views

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Q & A Q & A Code

⨘ } Math Equations in Keynote / LaTeX

Apple Keynote takes Latex format equations. Some useful commands are below. x^2 + y^2 = z^2 If you like to have subscripts x_n^2 + y_n^2 = z_n^2 Greek letters \alpha \beta \gamma \rho \sigma \delta \epsilon Operators \times \otimes \oplus \cup \cap < > \subset \supset \subseteq \supseteq \int \oint \sum \prod \times \div \cup […]

 329 total views

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Q & A Q & A VLSI

⨘ } How to use extract_model_split_partial_clock_gating_arc variable in PrimeTime ?

extract_model_split_partial_clock_gating_arc variable controls whether to split clock gating setup and hold arcs in extracted timing model (ETM). Default value of this variable is FALSE. Setting of this variable affects all formats e.g. synopsys database (.db), liberty (.lib) formats. This variable can be set to either TRUE or FALSE. FALSE: merges all clock gating checks and […]

 227 total views

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Tools

⨘ } Powerful charting tool for FOREX, CFDs, and Bitcoin

Realtime chart for FOREX, CFDs, and Bitcoin

 132 total views

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Q & A Q & A VLSI

⨘ } How do you fix a finite-state machine (digital logic, Verilog, logic gates, clock, small electronics, FSM, electronics)?

For small state-machines it might be easy by looking at it, however for bigger state machines and interlinked state-machines just by looking may not be easy to fix, there are EDA tools available which can identify stuck states, e.g. Mentor’s autocheck. Also by analyzing code coverage data one can review state machine coverage and identify […]

 246 total views

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Q & A Q & A Code

⨘ } clearcase version control useful commands

Set alias alias ct /usr/atria/bin/cleartool Version ct -ver List vob ct lsvob List views ct lsview ct lsview view-tag Create a tag ct mktag -view -tag tag-name Set a view ct setview view-name Print current view ct pwv List history ct lshistory file-name List private files ct lsprivate List checkout files ct lsco -r -l […]

 718 total views

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Q & A Q & A VLSI

⨘ } Clock domain crossings – Reconvergence – What to do?

Reconvergence – in simple terms signals are diverging from same end-point in Tx clock domain and going to multiple end-points in Rx clock domain(s). See attached fig. What can we do in this situation? First of all it is an important issue which needs to be carefully reviewed. There can be different approaches to mitigate […]

 275 total views

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Q & A Q & A Code

⨘ } vi / vim / gvim editor useful commands

Some common settings you may want to keep in .vimrc file set number set backspace=indent,eol,start set hlsearch set shiftwidth=3 set tabstop=3  768 total views

 768 total views

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Q & A Q & A VLSI

⨘ } Which ASIC language should I focus on? Verilog 2005, SystemVerilog, VHDL or other? “for ASIC SYNTHETIZABLE”.

Either is good. North American companies prefers Verilog/SystemVerilog and European companies prefer VHDL. Each has it own advantages and disadvantages. One need to know fundamentals of writing a good RTL code. Modern EDA tools can synthesize RTL code written in either language as long as synthesizable constructs are used. I have answered this question on […]

 262 total views

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Discuss

⨘ } Which one is better? A PhD or a 2nd master’s?

I think, one needs to know first where they want to see themselves 10–15 years future in life. Double Masters or PHD? well what I have seen is people got admission to PhD and due to circumstances they switch back to Masters. People who do not have clear direction they juggle here and there. Sometime […]

 279 total views

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Discuss

⨘ } How Hard is PhD ?

Totally depends on what is individual’s situation is. Typically it takes between 6–7 years in American reputed universities. Every university has some guidelines, among them a thesis is must with some publications. This is academic requirements. As long as one satisfies academic requirements university awards PhD. However one may not be doing or contributing to […]

 256 total views

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Q & A Q & A VLSI

⨘ } Is there any approach of automatically detect Async Fifo in scope of CDC ?

This question was asked by “Vazgen Gyoletsyan” on youtube leprofesseur channel. My impression is that modern CDC tools in their reports provide detailed information that can be scripted to know various information related to clock domain crossings in the full chip design.  666 total views

 666 total views

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Tools

⨘ } Real Time FOREX Calculator

Currency Converter by OANDA  322 total views

 322 total views

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Discuss Investments

⨘ } Greater Toronto’s Real Estate House Prices Setting Record – is there a signal before storm ?

Toronto’s house prices are touching record breaking heights since pandemic started. Is this a signal before storm ? What do you think – please leave your comments below. There are many things to consider. Toronto is the home for many immigrants families from all over the world and consistently attracted people from across the globe. […]

 871 total views

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Q & A Q & A Code

⨘ } extract a pattern from file – perl

#!/usr/bin/perl use strict; use warnings; open my $FH, ‘<‘, $ARGV[1] or die “Could not open file: $ARGV[1] $!\n”; open my $EXT_FH, ‘>’, $ARGV[2] or die “Could not open file: $ARGV[2] $!\n”; while (my $line = <$FH>){ if ($line =~ /cabist|tap|fscan|fbscan|dangle) print $EXT_FH $line; } close $FH; close $EXT_FH;  571 total views

 571 total views

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Q & A Q & A Code

⨘ } git version control useful commands

1. clone from repository git clone $GIT_REPOS/ip cloned-ip where: $GIT_REPOS is path to git repository if you like to have little fancy to organize cloned versions with dates, i prefer this way: git clone $GIT_REPOS/ip ip-`date +%Y%b%d-%H%M` also you can further use alias to have this command as: alias hrclone “$GIT_REPOS/ip ip-hr-‘date +%Y%b%d-%H%M’” 2. list […]

 834 total views

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Q & A Q & A Code

⨘ } Linux / Unix useful commands

1. compress and archive the directory / folder tar -zcvf /home/folder.tar.gz /home/folder where: z: compress archive using gzip program c: create archive on linux v: verbose, show progress on screen f: archive file name 2. secure copy from remote server to local scp user_name@ip_address:/home/folder/file /local_dir/copied_files/ 3. secure copy from local to remote server scp /local_dir/file […]

 696 total views

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Q & A Q & A Code

⨘ } recursive folder structure based on excel spreadsheet information – perl

Below a simple perl script to make directory folder structure which may be helpful for you if you need to deal with thousands of folders. Example: folder_structure.csv (you may extract csv fromat from excel sheet). We need to make folder structure as continent folder contains regions, regions contains countries, each country contains states etc. ASIA,SOUTH […]

 485 total views

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Business Investments

⨘ } Hedge fund strategies – in theory.

Hedge funds have become very popular among very wealthy communities as preferred medium of investment. To our knowledge there is no standard definition of hedge funds but common characteristics of hedge fund are: private investment fund which invest in variety of asset classes and employs a great variety of investment strategies. Even during 2008 market […]

 890 total views

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Discuss

⨘ } Banks vs Credit Unions – which is better for you ?

A brief discussion on Banks vs Credit unions. Banks: 1) Typical higher monthly account fees, e.g. $5-$10 for basic chequing account. There are difference types of accounts are offered by banks, chequing accounts are common, also bank changes fees for issuing cheques. 2) Banks do not typically give interests, if if they do they give […]

 1,167 total views

Categories
Computing VLSI

⨘ } VLSI } 20 } CMOS Interconnects }

Wire connecting the devices (nmos, pmos) are normally referred to as interconnects. Interconnects are very important, almost 70 percent chip area is consumed by interconnects. Interconnects increase circuit delays due to resistance and capacitances associated with them. Coupling capacitances induces crosstalk delay effects. Long wires induces inductive coupling due to inductance associated with them. Electric […]

 1,090 total views

Categories
Q & A Q & A Algorithms

⨘ } LUP Decomposition: why do we need the P? Why the LU will give us a wrong result?

“P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero element on U’s diagonal with only exception when all diagonal U are simultaneously zero.  2,795 total views

 2,795 total views

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Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?

In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must fulfill minimum pulse width requirements in the receiving faster clock domain. If source clock is minimum 1.5x slower than destination clock, it is safe, one does not need special logic in source domain. In both […]

 2,420 total views

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Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from slower clock (source domain) to faster clock (destination domain) which technique can be used?

When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, implementation must fulfill minimum pulse width requirements in slower clock. One may implement open loop state machine based solution in faster clock domain or some mechanism which makes sure to fulfill minimum pulse width requirement. […]

 2,374 total views

Categories
Q & A Q & A VLSI

⨘ } Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?

This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, something more deeper related to device physics.  2,934 total views

 2,934 total views

Categories
Q & A Q & A VLSI

⨘ } Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?

Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before using them in design. Many designers simply use 2 or 3 regular d – flops for synchronization which is not a good design practice. Frequency ratio has nothing to do with the number of sync […]

 2,713 total views

Categories
Q & A Q & A VLSI

⨘ } What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?

There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, second, we need to check whether data is passing from faster clock to slower or vice versa. We need to make sure of data stability as well, we need to understand intent of design and […]

 2,324 total views

Categories
Business Economics Q & A Q & A Economics

⨘ } Error with gEcon installation on Apple MAC

error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there before you try to make links,  2,858 total views

 2,858 total views

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Q & A Q & A VLSI

⨘ } Antenna Effects – Can jumpers be in higher and lower metal both?

different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it will increase net resistance and hence delay.  4,229 total views

 4,229 total views

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Q & A Q & A VLSI

⨘ } How tap cells remove latch-up?

n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library with uniform height (certain advantages such as reduce std cell size, and so pack more cells in a given area), means those cells in same row can share well-ties (done via TAP cells), which can […]

 3,201 total views,  5 views today

Categories
Computing VLSI

⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }

We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be verified. We discuss following topics: 1. Master asserts request signal to slave indicating communication initiation, and request signal should get asserted only after N number of clock cycles data signal is stable. 2. Slave’s grant […]

 1,548 total views

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Computing VLSI

⨘ } VLSI } 18 } Mentor’s Questa CDC Analysis } 0in }

Siemens / Mentor’s Questa 0-in clock domain crossing (CDC) solution – how to use Questa CDC tool, what are different clock domain crossing issues, different modes of operation of the tool, how to run the tool and generate CDC reports on full chip. Various aspects are discussed, e.g. what are common kinds of CDC violations, […]

 4,050 total views

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Computing VLSI

⨘ } VLSI } 017 } CMOS Power Consumption }

CMOS power and energy concepts, power analysis during chip design flow is discussed. AC and DC power are discussed. Different power components of PMOS and NMOS dynamic and static power are discussed. Static and Dynamic power equations are discussed. A brief overview of Apache Power Artist EDA power analysis tool is discussed. Dynamic power in […]

 3,603 total views

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Computing VLSI

⨘ } VLSI } 016 } Do You Write a Good RTL Code }

Important concepts for a good RTL design, blocking, non-blocking type of statements in verilog, multiple-drivers, assertions, fsm-deadlock, and in general good digital design practices are discussed. LEPROF/1LEPROF/LEPROFESSEUR  3,527 total views

 3,527 total views

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Computing VLSI

VLSI } 015 } Static Timing Analysis

This lecture discuss static timing analysis concepts. What are different paths, different kinds of checks, e.g. max type, min type timing analysis tool like prime time from synopsys does. How the setup and hold checks are performed, how to analyzed the timing report, how to fix the setup and hold violations are discussed. The need […]

 4,175 total views

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Computing VLSI

VLSI } 014 } Latch-up & CMOS Technologies }

Latch-up phenomenon in CMOS circuits – What is latch-up, what are typical methods to mitigate latch-up and layout changes for conventional bulk silicon technology. A discussion on other technology – SOI versus bulk silicon is presented.  5,270 total views

 5,270 total views

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Computing VLSI

VLSI } 013 } Floor-planning tips }

This lecture discusses some of the SoC floor-planning challenges and tips. A good floor-plan is the key to quality placement results. These are NP-hard problems which EDA tool have to deal with. A good initial floor-plan can save lot of physical design issues later in the design phase. It is very important to have a […]

 3,821 total views