Arts

History

• Perl script to make recursive folder structure based on excel spreadsheet information
  Below a simple perl script to make directory folder structure which may be helpful for you if you need to ...
• Hedge fund strategies – in theory.
  Hedge funds have become very popular among very wealthy communities as preferred medium of investment. To our knowledge there is ...
• Banks vs Credit Unions
  A brief discussion on Banks vs Credit unions. Banks: 1) Typical higher monthly account fees, e.g. $5-$10 for basic chequing account. There ...
• ⨘ } VLSI } 20 } Interconnects }
  https://youtu.be/CO_cdKcy23g Discussion on vlsi interconnects, interconnects play a major role and are very important, almost 70 percent chip area is consumed ...
• LUP Decomposition: why do we need the P? Why the LU will give us a wrong result?
  “P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero ...
• Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?
  In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must ...
• Clock Domain Crossing: When the data is crossing from slower(Source Clock) clock to faster clock(destination clock) which technique can be used?
  When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, ...
• Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?
  This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, ...
• Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?
  Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before ...
• What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?
  There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, ...
• Error with gEcon installation on Apple MAC
  error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there ...
• Antenna Effects – Can jumpers be in higher and lower metal both?
  different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it ...
• How tap cells remove latch-up?
  n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library ...
• ⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }
  We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be ...
• ⨘ } VLSI } 18 } Mentor’s Questa CDC Analysis } 0in }
  This lecture discusses Mentor’s Questa 0in CDC solution, how to use questa cdc tool, what are different clock domain crossing ...

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• 9
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Geography

• Perl script to make recursive folder structure based on excel spreadsheet information
  Below a simple perl script to make directory folder structure which may be helpful for you if you need to ...
• Hedge fund strategies – in theory.
  Hedge funds have become very popular among very wealthy communities as preferred medium of investment. To our knowledge there is ...
• Banks vs Credit Unions
  A brief discussion on Banks vs Credit unions. Banks: 1) Typical higher monthly account fees, e.g. $5-$10 for basic chequing account. There ...
• ⨘ } VLSI } 20 } Interconnects }
  https://youtu.be/CO_cdKcy23g Discussion on vlsi interconnects, interconnects play a major role and are very important, almost 70 percent chip area is consumed ...
• LUP Decomposition: why do we need the P? Why the LU will give us a wrong result?
  “P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero ...
• Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?
  In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must ...
• Clock Domain Crossing: When the data is crossing from slower(Source Clock) clock to faster clock(destination clock) which technique can be used?
  When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, ...
• Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?
  This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, ...
• Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?
  Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before ...
• What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?
  There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, ...
• Error with gEcon installation on Apple MAC
  error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there ...
• Antenna Effects – Can jumpers be in higher and lower metal both?
  different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it ...
• How tap cells remove latch-up?
  n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library ...
• ⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }
  We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be ...
• ⨘ } VLSI } 18 } Mentor’s Questa CDC Analysis } 0in }
  This lecture discusses Mentor’s Questa 0in CDC solution, how to use questa cdc tool, what are different clock domain crossing ...

• 1
• 2
• 3
• 4
• 5
• 6
...
• 9
• >>

Psychology

• Perl script to make recursive folder structure based on excel spreadsheet information
  Below a simple perl script to make directory folder structure which may be helpful for you if you need to ...
• Hedge fund strategies – in theory.
  Hedge funds have become very popular among very wealthy communities as preferred medium of investment. To our knowledge there is ...
• Banks vs Credit Unions
  A brief discussion on Banks vs Credit unions. Banks: 1) Typical higher monthly account fees, e.g. $5-$10 for basic chequing account. There ...
• ⨘ } VLSI } 20 } Interconnects }
  https://youtu.be/CO_cdKcy23g Discussion on vlsi interconnects, interconnects play a major role and are very important, almost 70 percent chip area is consumed ...
• LUP Decomposition: why do we need the P? Why the LU will give us a wrong result?
  “P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero ...
• Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?
  In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must ...
• Clock Domain Crossing: When the data is crossing from slower(Source Clock) clock to faster clock(destination clock) which technique can be used?
  When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, ...
• Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?
  This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, ...
• Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?
  Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before ...
• What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?
  There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, ...
• Error with gEcon installation on Apple MAC
  error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there ...
• Antenna Effects – Can jumpers be in higher and lower metal both?
  different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it ...
• How tap cells remove latch-up?
  n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library ...
• ⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }
  We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be ...
• ⨘ } VLSI } 18 } Mentor’s Questa CDC Analysis } 0in }
  This lecture discusses Mentor’s Questa 0in CDC solution, how to use questa cdc tool, what are different clock domain crossing ...

• 1
• 2
• 3
• 4
• 5
• 6
...
• 9
• >>

Literature

• Perl script to make recursive folder structure based on excel spreadsheet information
  Below a simple perl script to make directory folder structure which may be helpful for you if you need to ...
• Hedge fund strategies – in theory.
  Hedge funds have become very popular among very wealthy communities as preferred medium of investment. To our knowledge there is ...
• Banks vs Credit Unions
  A brief discussion on Banks vs Credit unions. Banks: 1) Typical higher monthly account fees, e.g. $5-$10 for basic chequing account. There ...
• ⨘ } VLSI } 20 } Interconnects }
  https://youtu.be/CO_cdKcy23g Discussion on vlsi interconnects, interconnects play a major role and are very important, almost 70 percent chip area is consumed ...
• LUP Decomposition: why do we need the P? Why the LU will give us a wrong result?
  “P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero ...
• Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?
  In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must ...
• Clock Domain Crossing: When the data is crossing from slower(Source Clock) clock to faster clock(destination clock) which technique can be used?
  When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, ...
• Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?
  This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, ...
• Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?
  Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before ...
• What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?
  There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, ...
• Error with gEcon installation on Apple MAC
  error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there ...
• Antenna Effects – Can jumpers be in higher and lower metal both?
  different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it ...
• How tap cells remove latch-up?
  n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library ...
• ⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }
  We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be ...
• ⨘ } VLSI } 18 } Mentor’s Questa CDC Analysis } 0in }
  This lecture discusses Mentor’s Questa 0in CDC solution, how to use questa cdc tool, what are different clock domain crossing ...

• 1
• 2
• 3
• 4
• 5
• 6
...
• 9
• >>