This lecture discusses timing in digital circuits.
It is said that “Timing is everything”. If someone does not arrive on time at a meeting of a party it is considered bad effect. In similar way timing is the most important in digital circuits. Sequential digital techniques are dependent on correct time accurate behavior of design elements out of which flip-flops or memory elements are quite tricky in terms of timing. This lecture discuss flip-flop set-up, hold-time requirements, design solutions for meeting timing goals when designing integrated circuits. If data does not arrive in time, it will fail the logic and chip will not work!
In simple form one can understand that set-up time of flip-flop is associated with clock which hold-time is associated with data. When aking circuit changes for set-up time, one need to consider or pay attention to clock time period, duty cycle etc. or simple words input signal arrive in the set-up time window at flip flop and it may lead to incorrect behavior as flip-flop may suffer from meta-stability. For hold violation, one nees to pay attention to data path. If there is hold-violation it means that data path is too short and the data which need to be available on next clock cycle is arriving in the current cycle and flip-flop with register wrong value. By increasing data path one may solve hold-violation. However once hold violations are fixed then it may lead to set-up violations. So a careful selection of points for inserting buffers need to be done for fixing hold violations. It is difficult to solve set-up violations, mostly it is to lower clock period.
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