CODE
- ⨘ } awk miscellaneous commands 8th April 20211. Extract pattern from file and do sum of all entries matching the pattern grep ” Sequential ” idle_power.txt ...
- ⨘ } Math Equations in Keynote / LaTeX 2nd April 2021Apple Keynote takes Latex format equations. Some useful commands are below. x^2 + y^2 = z^2 If you like to have subscripts x_n^2 ...
- ⨘ } clearcase version control useful commands 29th March 2021Set alias alias ct /usr/atria/bin/cleartool Version ct -ver List vob ct lsvob List views ct lsview ct lsview view-tag Create a tag ct mktag -view -tag ...
- ⨘ } vi / vim / gvim editor useful commands 28th March 2021Some common settings you may want to keep in .vimrc file set number set backspace=indent,eol,start set hlsearch set shiftwidth=3 set tabstop=3 5,511 total views, 5 views today
- ⨘ } extract a pattern from file – perl 26th March 2021#!/usr/bin/perl use strict; use warnings; open my $FH, ‘<‘, $ARGV $!\n”; open my $EXT_FH, ‘>’, $ARGV or ...
- ⨘ } git version control useful commands 26th March 20211. clone from repository git clone $GIT_REPOS/ip cloned-ip where: $GIT_REPOS is path to git repository if you like to ...
- ⨘ } Linux / Unix useful commands 24th March 20211. compress and archive the directory / folder tar -zcvf /home/folder.tar.gz /home/folder where: z: compress archive using gzip program c: create ...
- ⨘ } recursive folder structure based on excel spreadsheet information – perl 24th January 2021Below a simple perl script to make directory folder structure which may be helpful for you if you need to ...
- ⨘ } vi Editor: quick guide } 8th February 2016This lecture provides a quick overview of vi editor. 6,935 total views, 2 views today
VLSI
- ⨘ } How to use extract_model_split_partial_clock_gating_arc variable in PrimeTime ? 31st March 2021extract_model_split_partial_clock_gating_arc variable controls whether to split clock gating setup and hold arcs in extracted timing model (ETM). Default value of ...
- ⨘ } How do you fix a finite-state machine (digital logic, Verilog, logic gates, clock, small electronics, FSM, electronics)? 30th March 2021For small state-machines it might be easy by looking at it, however for bigger state machines and interlinked state-machines just ...
- ⨘ } Clock domain crossings – Reconvergence – What to do? 29th March 2021Reconvergence – in simple terms signals are diverging from same end-point in Tx clock domain and going to multiple end-points ...
- ⨘ } Which ASIC language should I focus on? Verilog 2005, SystemVerilog, VHDL or other? “for ASIC SYNTHETIZABLE”. 28th March 2021Either is good. North American companies prefers Verilog/SystemVerilog and European companies prefer VHDL. Each has it own advantages and disadvantages. ...
- ⨘ } Is there any approach of automatically detect Async Fifo in scope of CDC ? 26th March 2021This question was asked by “Vazgen Gyoletsyan” on youtube leprofesseur channel. My impression is that modern CDC tools in their reports ...
- ⨘ } Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used? 8th November 2019In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must ...
- ⨘ } Clock Domain Crossing: When the data is crossing from slower clock (source domain) to faster clock (destination domain) which technique can be used? 8th November 2019When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, ...
- ⨘ } Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset? 8th November 2019This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, ...
- ⨘ } Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio? 8th November 2019Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before ...
- ⨘ } What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations? 8th November 2019There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, ...
- ⨘ } Antenna Effects – Can jumpers be in higher and lower metal both? 7th November 2019different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it ...
- ⨘ } How tap cells remove latch-up? 7th November 2019n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library ...
ALGORITHMS
- ⨘ } LUP Decomposition: why do we need the P? Why the LU will give us a wrong result? 8th November 2019“P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero ...
ECONOMICS
- ⨘ } Error with gEcon installation on Apple MAC 8th November 2019error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there ...
6,976 total views, 4 views today