- Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?
- Clock Domain Crossing: When the data is crossing from slower(Source Clock) clock to faster clock(destination clock) which technique can be used?
- Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?
- Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?
- What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?
- Antenna Effects – Can jumpers be in higher and lower metal both?
- How tap cells remove latch-up?
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