For small state-machines it might be easy by looking at it, however for bigger state machines and interlinked state-machines just by looking may not be easy to fix, there are EDA tools available which can identify stuck states, e.g. Mentor’s autocheck. Also by analyzing code coverage data one can review state machine coverage and identify which states are potentially stuck. Once states are identified its easier to fix. Often it’s better practice to go to some default. Also one can write assertions which can further help.
Someone asked this question on Quora where I replied: https://www.quora.com/How-do-you-fix-a-finite-state-machine-digital-logic-Verilog-logic-gates-clock-small-electronics-FSM-electronics
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