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Q & A Q & A VLSI

⨘ } How to use extract_model_split_partial_clock_gating_arc variable in PrimeTime ?

extract_model_split_partial_clock_gating_arc variable controls whether to split clock gating setup and hold arcs in extracted timing model (ETM). Default value of this variable is FALSE. Setting of this variable affects all formats e.g. synopsys database (.db), liberty (.lib) formats. This variable can be set to either TRUE or FALSE. FALSE: merges all clock gating checks and […]

 995 total views,  4 views today

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Q & A Q & A VLSI

⨘ } How do you fix a finite-state machine (digital logic, Verilog, logic gates, clock, small electronics, FSM, electronics)?

For small state-machines it might be easy by looking at it, however for bigger state machines and interlinked state-machines just by looking may not be easy to fix, there are EDA tools available which can identify stuck states, e.g. Mentor’s autocheck. Also by analyzing code coverage data one can review state machine coverage and identify […]

 946 total views,  2 views today

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Q & A Q & A VLSI

⨘ } Clock domain crossings – Reconvergence – What to do?

Reconvergence – in simple terms signals are diverging from same end-point in Tx clock domain and going to multiple end-points in Rx clock domain(s). See attached fig. What can we do in this situation? First of all it is an important issue which needs to be carefully reviewed. There can be different approaches to mitigate […]

 1,729 total views,  8 views today

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Q & A Q & A VLSI

⨘ } Which ASIC language should I focus on? Verilog 2005, SystemVerilog, VHDL or other? “for ASIC SYNTHETIZABLE”.

Either is good. North American companies prefers Verilog/SystemVerilog and European companies prefer VHDL. Each has it own advantages and disadvantages. One need to know fundamentals of writing a good RTL code. Modern EDA tools can synthesize RTL code written in either language as long as synthesizable constructs are used. I have answered this question on […]

 946 total views

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Q & A Q & A VLSI

⨘ } Is there any approach of automatically detect Async Fifo in scope of CDC ?

This question was asked by “Vazgen Gyoletsyan” on youtube leprofesseur channel. My impression is that modern CDC tools in their reports provide detailed information that can be scripted to know various information related to clock domain crossings in the full chip design.  2,526 total views,  10 views today

 2,526 total views,  10 views today

Categories
Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?

In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must fulfill minimum pulse width requirements in the receiving faster clock domain. If source clock is minimum 1.5x slower than destination clock, it is safe, one does not need special logic in source domain. In both […]

 4,205 total views

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Q & A Q & A VLSI

⨘ } Clock Domain Crossing: When the data is crossing from slower clock (source domain) to faster clock (destination domain) which technique can be used?

When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, implementation must fulfill minimum pulse width requirements in slower clock. One may implement open loop state machine based solution in faster clock domain or some mechanism which makes sure to fulfill minimum pulse width requirement. […]

 3,975 total views,  5 views today

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Q & A Q & A VLSI

⨘ } Why will the second flop go into meta stable state in the first place? If we reset the first flop, the data will be 0 , so will the second flop not just capture the 0 though it’s not reset?

This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, something more deeper related to device physics.  4,584 total views

 4,584 total views

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Q & A Q & A VLSI

⨘ } Is there any formula/approach for finding the required number of extra flops (2 or 3 or more) at receiving domain, based on the clock frequency ratio?

Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before using them in design. Many designers simply use 2 or 3 regular d – flops for synchronization which is not a good design practice. Frequency ratio has nothing to do with the number of sync […]

 4,267 total views,  5 views today

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Q & A Q & A VLSI

⨘ } What happens when CDC is between two synchronous clock domain(ex- clk1 and clk2= clk1/2)? Can there be violations?

There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, second, we need to check whether data is passing from faster clock to slower or vice versa. We need to make sure of data stability as well, we need to understand intent of design and […]

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Q & A Q & A VLSI

⨘ } Antenna Effects – Can jumpers be in higher and lower metal both?

different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it will increase net resistance and hence delay.  6,020 total views,  15 views today

 6,020 total views,  15 views today

Categories
Q & A Q & A VLSI

⨘ } How tap cells remove latch-up?

n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library with uniform height (certain advantages such as reduce std cell size, and so pack more cells in a given area), means those cells in same row can share well-ties (done via TAP cells), which can […]

 5,964 total views