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Transmission gate logic style offers certain advantages over pass-transistor logic. We discuss about transmission logic gate concepts, how can we design circuits using transmission gates, what are key advantages, disadvantages of transmission gates over traditional logic and pass-transistor logic styles with an example circuit design. Thanks for watching. ► SUBSCRIBE, Like 👍 , and press […]
1,185 total views, 8 views today
Realtime chart for stocks
735 total views, 1 views today
nmos/pmos transistors can be used in a configuration where voltage on gate can be think in terms of control or valve to pass water (electric current analogue) between terminals of transistor, pass-transistors logic concepts are discussed. How pass transistors are different than conventional CMOS logic circuits, advantages, disadvantages of pass-transistor logic are discussed with examples […]
790 total views, 2 views today
Complex Concepts Made Easy – LEPROFESSEUR / LEPROF / 1LEPROF 1,144 total views, 6 views today
1,144 total views, 6 views today
Analytical Hierarchy Process (AHP) is a well known method for making qualitative decisions. AHP provides formal technique for evaluating alternatives in presence of different criteria or attributes. Satty’s (1980) AHP technique is a pairwise comparison method which tries to capture relative judgements about attributes and alternative in a matrix form that ensure consistency. The simplicity […]
1,120 total views, 6 views today
1. Extract pattern from file and do sum of all entries matching the pattern grep ” Sequential ” idle_power.txt | awk ‘{sum += $3} END {print sum}’ Here $3 is which column is to get sum of. Idea is to grep a certain pattern from file from each line and then process output by awk […]
2,119 total views, 10 views today
We have discussed logic gates in the previous lecture: Logic gates using multiplexers. We discussed at logic gate level. In this lecture we gonna be discussing next level – gate circuits. Techniques to design logic gate circuits using nmos and pmos. Concepts of CMOS circuit design with nMOS and pMOS are discussed. We can think […]
720 total views, 6 views today
Apple Keynote takes Latex format equations. Some useful commands are below. x^2 + y^2 = z^2 If you like to have subscripts x_n^2 + y_n^2 = z_n^2 Greek letters \alpha \beta \gamma \rho \sigma \delta \epsilon Operators \times \otimes \oplus \cup \cap < > \subset \supset \subseteq \supseteq \int \oint \sum \prod \times \div \cup […]
1,732 total views, 4 views today
extract_model_split_partial_clock_gating_arc variable controls whether to split clock gating setup and hold arcs in extracted timing model (ETM). Default value of this variable is FALSE. Setting of this variable affects all formats e.g. synopsys database (.db), liberty (.lib) formats. This variable can be set to either TRUE or FALSE. FALSE: merges all clock gating checks and […]
663 total views, 4 views today
Realtime chart for FOREX, CFDs, and Bitcoin
358 total views, 1 views today
For small state-machines it might be easy by looking at it, however for bigger state machines and interlinked state-machines just by looking may not be easy to fix, there are EDA tools available which can identify stuck states, e.g. Mentor’s autocheck. Also by analyzing code coverage data one can review state machine coverage and identify […]
634 total views
Set alias alias ct /usr/atria/bin/cleartool Version ct -ver List vob ct lsvob List views ct lsview ct lsview view-tag Create a tag ct mktag -view -tag tag-name Set a view ct setview view-name Print current view ct pwv List history ct lshistory file-name List private files ct lsprivate List checkout files ct lsco -r -l […]
3,019 total views, 15 views today
Reconvergence – in simple terms signals are diverging from same end-point in Tx clock domain and going to multiple end-points in Rx clock domain(s). See attached fig. What can we do in this situation? First of all it is an important issue which needs to be carefully reviewed. There can be different approaches to mitigate […]
904 total views, 2 views today
Some common settings you may want to keep in .vimrc file set number set backspace=indent,eol,start set hlsearch set shiftwidth=3 set tabstop=3 3,036 total views, 20 views today
3,036 total views, 20 views today
Either is good. North American companies prefers Verilog/SystemVerilog and European companies prefer VHDL. Each has it own advantages and disadvantages. One need to know fundamentals of writing a good RTL code. Modern EDA tools can synthesize RTL code written in either language as long as synthesizable constructs are used. I have answered this question on […]
636 total views
I think, one needs to know first where they want to see themselves 10–15 years future in life. Double Masters or PHD? well what I have seen is people got admission to PhD and due to circumstances they switch back to Masters. People who do not have clear direction they juggle here and there. Sometime […]
620 total views, 2 views today
Totally depends on what is individual’s situation is. Typically it takes between 6–7 years in American reputed universities. Every university has some guidelines, among them a thesis is must with some publications. This is academic requirements. As long as one satisfies academic requirements university awards PhD. However one may not be doing or contributing to […]
624 total views
This question was asked by “Vazgen Gyoletsyan” on youtube leprofesseur channel. My impression is that modern CDC tools in their reports provide detailed information that can be scripted to know various information related to clock domain crossings in the full chip design. 1,681 total views
1,681 total views
Currency Converter by OANDA 836 total views
836 total views
Toronto’s house prices are touching record breaking heights since pandemic started. Is this a signal before storm ? What do you think – please leave your comments below. There are many things to consider. Toronto is the home for many immigrants families from all over the world and consistently attracted people from across the globe. […]
3,654 total views, 15 views today
#!/usr/bin/perl use strict; use warnings; open my $FH, ‘<‘, $ARGV[1] or die “Could not open file: $ARGV[1] $!\n”; open my $EXT_FH, ‘>’, $ARGV[2] or die “Could not open file: $ARGV[2] $!\n”; while (my $line = <$FH>){ if ($line =~ /cabist|tap|fscan|fbscan|dangle) print $EXT_FH $line; } close $FH; close $EXT_FH; 1,607 total views, 10 views today
1,607 total views, 10 views today
1. clone from repository git clone $GIT_REPOS/ip cloned-ip where: $GIT_REPOS is path to git repository if you like to have little fancy to organize cloned versions with dates, i prefer this way: git clone $GIT_REPOS/ip ip-`date +%Y%b%d-%H%M` also you can further use alias to have this command as: alias hrclone “$GIT_REPOS/ip ip-hr-‘date +%Y%b%d-%H%M’” 2. list […]
2,809 total views, 15 views today
1. compress and archive the directory / folder tar -zcvf /home/folder.tar.gz /home/folder where: z: compress archive using gzip program c: create archive on linux v: verbose, show progress on screen f: archive file name 2. secure copy from remote server to local scp user_name@ip_address:/home/folder/file /local_dir/copied_files/ 3. secure copy from local to remote server scp /local_dir/file […]
1,686 total views, 5 views today
Below a simple perl script to make directory folder structure which may be helpful for you if you need to deal with thousands of folders. Example: folder_structure.csv (you may extract csv fromat from excel sheet). We need to make folder structure as continent folder contains regions, regions contains countries, each country contains states etc. ASIA,SOUTH […]
1,034 total views, 2 views today
Hedge funds have become very popular among very wealthy communities as preferred medium of investment. To our knowledge there is no standard definition of hedge funds but common characteristics of hedge fund are: private investment fund which invest in variety of asset classes and employs a great variety of investment strategies. Even during 2008 market […]
1,798 total views, 15 views today
A brief discussion on Banks vs Credit unions. Banks: 1) Typical higher monthly account fees, e.g. $5-$10 for basic chequing account. There are difference types of accounts are offered by banks, chequing accounts are common, also bank changes fees for issuing cheques. 2) Banks do not typically give interests, if if they do they give […]
2,152 total views
Wire connecting the devices (nmos, pmos) are normally referred to as interconnects. Interconnects are very important, almost 70 percent chip area is consumed by interconnects. Interconnects increase circuit delays due to resistance and capacitances associated with them. Coupling capacitances induces crosstalk delay effects. Long wires induces inductive coupling due to inductance associated with them. Electric […]
2,109 total views, 10 views today
“P” i.e. partial pivoting, by using that strategy we improve stability of LU, and avoid the problem of having zero element on U’s diagonal with only exception when all diagonal U are simultaneously zero. 3,669 total views, 5 views today
3,669 total views, 5 views today
In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must fulfill minimum pulse width requirements in the receiving faster clock domain. If source clock is minimum 1.5x slower than destination clock, it is safe, one does not need special logic in source domain. In both […]
3,461 total views, 5 views today
When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, implementation must fulfill minimum pulse width requirements in slower clock. One may implement open loop state machine based solution in faster clock domain or some mechanism which makes sure to fulfill minimum pulse width requirement. […]
3,210 total views
This is probabilistic, please watch metastability lecture for more understanding. Keep in mind this is inherent problem with synchronous design, something more deeper related to device physics. 3,850 total views, 5 views today
3,850 total views, 5 views today
Different technology nodes have different requirements for sync flops. It needs to be characterized sync flops for various parameters before using them in design. Many designers simply use 2 or 3 regular d – flops for synchronization which is not a good design practice. Frequency ratio has nothing to do with the number of sync […]
3,517 total views
There may be violations, we need to see the origin of both clocks, both clocks need to be phase aligned, second, we need to check whether data is passing from faster clock to slower or vice versa. We need to make sure of data stability as well, we need to understand intent of design and […]
3,299 total views, 10 views today
error: unable to load shared object ‘/Library/Frameworks/R.framework/Versions/3.4/Resources/library/gEcon/libs/gEcon.so’ try setting up links, e.g. ln -s /Library/Frameworks/R.framework/Versions/3.5 /Library/Frameworks/R.framework/Versions/3.5 make sure all subdirectories are there before you try to make links, 4,153 total views
4,153 total views
different other techniques may be used, e.g. jog to upper layers, jog to lower layers might not help as it will increase net resistance and hence delay. 5,200 total views, 5 views today
5,200 total views, 5 views today
n-well and p-well are needed to tie to known potential, typically placement of standard cells is done via TAP-LESS library with uniform height (certain advantages such as reduce std cell size, and so pack more cells in a given area), means those cells in same row can share well-ties (done via TAP cells), which can […]
4,401 total views, 10 views today
We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be verified. We discuss following topics: 1. Master asserts request signal to slave indicating communication initiation, and request signal should get asserted only after N number of clock cycles data signal is stable. 2. Slave’s grant […]
2,385 total views, 8 views today
Siemens / Mentor’s Questa 0-in clock domain crossing (CDC) solution – how to use Questa CDC tool, what are different clock domain crossing issues, different modes of operation of the tool, how to run the tool and generate CDC reports on full chip. Various aspects are discussed, e.g. what are common kinds of CDC violations, […]
4,989 total views, 8 views today
CMOS power and energy concepts, power analysis during chip design flow is discussed. AC and DC power are discussed. Different power components of PMOS and NMOS dynamic and static power are discussed. Static and Dynamic power equations are discussed. A brief overview of Apache Power Artist EDA power analysis tool is discussed. Dynamic power in […]
4,438 total views, 6 views today
Important concepts for a good RTL design, blocking, non-blocking type of statements in verilog, multiple-drivers, assertions, fsm-deadlock, and in general good digital design practices are discussed. LEPROF/1LEPROF/LEPROFESSEUR 4,433 total views, 9 views today
4,433 total views, 9 views today
This lecture discuss static timing analysis concepts. What are different paths, different kinds of checks, e.g. max type, min type timing analysis tool like prime time from synopsys does. How the setup and hold checks are performed, how to analyzed the timing report, how to fix the setup and hold violations are discussed. The need […]
4,626 total views, 4 views today
Latch-up phenomenon in CMOS circuits – What is latch-up, what are typical methods to mitigate latch-up and layout changes for conventional bulk silicon technology. A discussion on other technology – SOI versus bulk silicon is presented. 5,608 total views, 2 views today
5,608 total views, 2 views today
This lecture discusses some of the SoC floor-planning challenges and tips. A good floor-plan is the key to quality placement results. These are NP-hard problems which EDA tool have to deal with. A good initial floor-plan can save lot of physical design issues later in the design phase. It is very important to have a […]
4,174 total views, 2 views today