⨘ } VLSI } 19 } System Verilog } Assertions } Async Interfaces } Protocol Verification }
We discuss assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be verified. We discuss following topics:
1. Master asserts request signal to slave indicating communication initiation, and request signal should get asserted only after N number of clock cycles data signal is stable.
2. Slave’s grant signal follows the request of master, that is grant should get de-asserted within N number of clock cycles of de-assertion of request signal from Master.
3. Assertion module.
4. Binding of assertion module to module instances.
5. Assertion controls – helpful for debugging.
1. At time 5:20 I misstated, I was supposed to say grant must have to be de-asserted within 2 clocks of req get de-asserted.
2. There is a mistake in module my_assertion code, it needs to have following.
input clk, rst, sel, req, grant, data;
Welcome to LEPROFESSEUR youtube channel. Please [ ►Subscribe ], and Also, remember to give thumbs up 👍 and press bell 🔔.
We appreciate your feedback and support.
Best, HR | 1LE PROF | LEPROF | LEPROFESSEUR }
214 total views, 2 views today