VLSI } 014 } Latch-up & CMOS Technologies }

This lecture presents latch-up phenomenon in SMOS circuits. What is latch-up, what are typical methods to mitigate latch-up and layout changes for conventional bulk silicon technology. A discussion on other technology – SOI versus bulk silicon is presented.

1,724 total views, 2 views today

One thought on “VLSI } 014 } Latch-up & CMOS Technologies }

  1. max

    sir can you explain a little more about current impulse and when you put the sio2 layer on the substrate wouldn’t it affect the threshold voltage and about the guard ring are they connected to the vss terminal ?

Leave a Reply

Your email address will not be published. Required fields are marked *

This site uses Akismet to reduce spam. Learn how your comment data is processed.

 

 

 

 

www.youtube.com/Leprofesseur

 

Knowledge at your fingertips } Rethink the way you learn }™     Leprofesseur }
Skip to toolbar