VLSI } 013 } Floor-planning tips }
This lecture discusses some of the SoC floor-planning challenges and tips. A good floor-plan is the key to quality placement results. These are NP-hard problems which EDA tool have to deal with. A good initial floor-plan can save lot of physical design issues later in the design phase. It is very important to have a good floor-plan done. What is a better placement for always-on blocks, where analog IPs can be placed for better results, some tips for floor-planning and placement are discussed in this lecture. A typical backend floor-plan flow steps are discussed.
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