VLSI } 009 } Clock Domain Crossings } FIFO }
This lecture extends the discussion on clock domain crossings. In this lecture design techniques for multi-bit clock crossings have been discussed. One can classify CDC signals in two groups broadly: control signals and data signals. For single bit control signals double flop synchronizing circuits or special library sync cells can be used safely. This becomes tricky if there are many signals (e.g. data bus) crossing the clocks. Two popular methods – FIFO (asynchronous FIFO, 2-deep FIFO), and MCP (multi-cycle paths) implementation techniques are heavily used in industry for CDC signals. This lecture discusses both techniques with a simple example.
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