Computing VLSI

⨘ } VLSI } 18 } Mentor’s Questa CDC Analysis } 0in }

Siemens / Mentor’s Questa 0-in clock domain crossing (CDC) solution – how to use Questa CDC tool, what are different clock domain crossing issues, different modes of operation of the tool, how to run the tool and generate CDC reports on full chip. Various aspects are discussed, e.g. what are common kinds of CDC violations, e.g. no_sync, combo_logic, multi_bits, reconvergence etc., what kind of analysis can be done by cdc tool, what are key points to take care of when performing CDC analysis on full chip.

Clock domain, Reset domain, and Power domain crossings are important to understand. All of these require synchronization of signal(s) from Tx (send) domain to Rx (receive) domain. It needs to be careful while integrating different IPs in SOC for these issues otherwise chip may not work as intended in silicon. Careful design techniques and design reviews are needed before chip design sign-off for pattern generation.

Modern EDA tools help to uncover those crossing paths which then need to be analyzed and take appropriate action by designers. Mentor’s Questa/0-in is considered as industry standard CDC sign-off tool. However Synopsys and Candence also provide CDC solutions.

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